HpW Tech 6: Jitter Fs/4 signal & LSB Toggle at Fs/192

The signal is based from Julian Dunn proposed in an AES paper. It has the sine base frequency at Fs/4 (11.025 kHz) and a LSB toggle (equal Square wave) at Fs/192 (~ 229 Hz).



The Digital Spectrum interpretation:

- 16 Bit Digital source !
- Clear sine Fs/4 (usual at -10dB using DAC/ADC)
- DC at -96.3 dB = 20 * log (1/2^16) caused from LSB energy
- 1. Harmonic of LSB toggle at 229 Hz at -96.3 dB = 20 * log (1/2^16)
- n Harmonic of LSB toggle at n * 229 Hz with given decay of square wave
- You will have a more or less with same level symmetric pins around the center Fs/4 peak (+/- half of 229 Hz) and then repeating bins with 229 Hz.


Now measure on Analog (DAC/ADC):
- Set the wave generation to 16 Bit (no dither is applied)
- Set the wave generation output level to -10 dB
- Set the sound card output level to maximum
- May use only one channel to avoid cross talk influences
- Record the signal if possible with higher bit resolution!
- Made first measurements to get the recording level right
- Now, measure with averaging (geometric) about 16 times should be OK or use your own NR's


ANALOG RESULT:
- You should have a more or less with same level symmetric pins around the center Fs/4 peak (+/- 229 Hz) and then repeating bins with 2 * 229 Hz.
- Other side peak's or raised noise may result from IM
- Other symmetric pins result from a FM/PM based clock jitter or even from a vibration of the crystal (very narrow peaks)
- If you miss any of the harmonics given from the LSB toggle the DAC/ADC resolution & linearity is may not able to reproduce this low level signal

Advanced issues on Analog:
- May use different sample rate the output sample rate to avoid same clock jitter given from the base crystal for the ADC & DAC.